1. Field of the Invention
The present invention relates to a method for processing a semiconductor wafer. In particular, the present invention relates to shortening a process of processing a semiconductor wafer achieving high breakdown voltage and low on-resistance and to a method for processing a semiconductor wafer with improved characteristics.
2. Description of the Related Art
As a silicon semiconductor wafer achieving high breakdown voltage and low on-resistance, known is a wafer structure in which pillar-like p type semiconductor regions and n type semiconductor regions are provided so as to form multiple pn junctions vertical to a wafer surface. This technology is described for instance in International Patent Publication No. WO02/067333, Pamphlet.
In this structure, when dopant concentrations and widths of the p type semiconductor regions and n type semiconductor regions are selected to be desired values, high breakdown voltage can be achieved in the pn junctions under application of reverse voltage. In the following, the description will be given by referring to such a structure as a super junction structure.
By referring to FIGS. 10A and 10B, and 11A to 11C, examples of a method for processing a semiconductor wafer with a super junction structure will be described.
As shown in FIG. 10A, an n+ type semiconductor substrate 11 is prepared, and an n type semiconductor layer (epitaxial layer) 12′ with a thickness of approximately 6 μm, for example, is stacked on a surface of the substrate 11. Subsequently, a mask with openings at predetermined intervals is disposed on the layer 12′. Then, ions of a p type impurity are implanted into the openings to form p type semiconductor regions 13′.
After that, the step of stacking the n type semiconductor layers 12′ (epitaxial growth) and the step of implanting ions of the p type impurity are repeated, for example, for seven times, to form a multi-layered epitaxial layer with a desired thickness (for example, approximately 42 μm). Finally, the ions of the p type impurity are diffused; thereby a wafer 20 with a super junction structure in which pillar-like n type semiconductor regions 12 and p type semiconductor regions 13 are alternately arranged is formed (FIG. 10B).
The following method is also known.
As shown in FIGS. 11A to 11C, an n type semiconductor layer (epitaxial layer) 22 with a desired thickness is stacked on an n+ type semiconductor substrate 21, for example, and multiple trenches 23 are then formed, so that pillar-like n type semiconductor layers remain (FIG. 1A). Thereafter, ions of a p type impurity are implanted obliquely into portions of the n type semiconductor layers 22, the portions exposed on the side walls of the trenches 23, to form pillar-like p type semiconductor regions 24 (FIG. 11B). Furthermore, insulating films 25 are buried respectively in positions between p type semiconductor regions 24. Thereby, a wafer 30 with a super junction structure is obtained (FIG. 11C).
As shown in FIGS. 10A and 10B, the conventional method for obtaining a wafer with a super junction structure requires the step of forming multiple epitaxial layers so as to stack the epitaxial layers in a thickness direction of the semiconductor wafer and the steps of ion implantation and diffusion. Thus, the conventional method has a problem that an extremely large number of processing steps are required.
In addition, the pillar-like semiconductor regions each have a shape in which multiple impurity diffusion regions are stacked. Accordingly, the side surfaces of the pillars (pn junctions) each have an undulate form. Thus, there is a problem that a depletion layer hardly spreads uniformly in a precise sense.
In a case of the method in which one portion of the pillar-like semiconductor layer is formed by oblique ion implantation as shown in FIGS. 11A to 11C, the trenches are each required to have a large width as shown in FIG. 11A, in order to have a uniform impurity profile of, for example, the p type semiconductor layer formed by the ion implantation, in a vertical direction to the wafer. For this reason, it is difficult to arrange multiple super junction structures in the wafer.